Embodiments of the inventive concept described herein relate to a method for reducing contact resistance by using a GST layer.
Along the gradual scaling-down of semiconductor devices in the past years, those devices are eventually meeting physical limits in improving their functionality. In other words, since the traditional Si-based device fabrication technology has come to be hardly regarded as providing more functional semiconductor devices, many efforts are going to find the next-generation high performance devices.
For example, the III-V compound semiconductors such as GaAs, AlGaAs, and InGaAs are recently used even for fabricating the semiconductor devices such as Field Effect Transistors (FET), High Electron Mobility Transistors (HEMT), and Hetero Junction Bipolar Transistors (HBT). Among them, InGaAs is spotlighted as a prospective one for a new substrate material.
In employing a new-generational high performance device, it is necessary to prepare very low resistance at junctions between metals and a substrate. A self-aligned Ni—InGaAs may provide several advantages in overcoming the issue about contact resistance. Therefore, many laboratories and companies are actively proceeding to find methodologies for reducing contact resistance by utilizing Ni—InGaAs.